The present invention relates to a semiconductor device and, in particular, it relates to a technique effectively applicable to a semiconductor device having a FINFET.
In these years, in LSI (Large Scale Integration) using silicon, the dimension of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) being a component thereof, particularly the gate length of a gate electrode has been decreasing steadily. The miniaturization of the MISFET has been advanced in a style conforming to the scaling law but, with respective progresses of the device generation, various problems have appeared, and it has becomes difficult to satisfy both the suppression of the short channel effect and the securing of a high-current driving capability of the MISFET. Consequently, research and development for new structure devices, which may replace the ordinary planer type MISFET, are being actively conducted.
The FINFET is one of the aforementioned new structure devices, and is a three dimensional configuration MISFET differing from the planer type MISFET.
For example, Patent Document 1 below discloses a FINFET in which fin resistance between a gate and a source region becomes small and capacitance between the gate and a drain region becomes small. To be specific, there is illustrated the FINFET in which a gate conductor is arranged over a fin at a position closer to the source region than to the drain region.
[Patent Document 1]
    International Publication No. WO2007/019023